Conventional semiconductor memory devices, for example, flash memory devices compare a current of a reference cell with a current of a memory cell using a sense amplifier, and use the results of the comparison to identify whether the memory cell is a program cell or an erase cell. Conventionally, when programming memory cells in a flash memory device, programming and verifying a reference cell in the flash memory device (hereinafter, referred to as “reference cell trimming”) may be needed to adjust a program voltage of the reference cell to a desired level. Such reference cell trimming may be performed by manufacturing engineers during fabrication of conventional flash memory devices.
FIG. 1 is a flowchart of a conventional method for trimming a reference cell in a semiconductor memory device. Referring to FIG. 1, in the conventional method, reference cell trimming may be performed using a bias current (or a bias voltage) input from a tester via an input/output (I/O) pad in the semiconductor memory device.
At S110, automatic trimming is performed on the reference cell. For example, the reference cell may be erased and programmed based on a given program bias voltage at S112. The reference cell may be implemented in the form of a transistor in which a source-drain current (hereinafter, referred to as a “reference cell current”) flows based on the program bias voltage. For example, a given bias voltage greater than a bias voltage applied to a source region may be applied to a drain region and a gate of the reference cell to program the reference cell. At S114, the programmed reference cell may be verified based on an external bias current input from a tester. For example, the reference cell current may be compared with the external bias current and completion of the verification of the reference cell may be determined based on a result of the comparison. The programming and verification of the reference cell may be repeated until the reference cell current is within a given error range of the external bias current.
The programming and verification may be automatically performed in the semiconductor memory device and referred to as automatic trimming (e.g., S112 and S114).
At S120, a tester measures the reference cell current flowing in the reference cell. When the reference cell current measured by the tester is within the given error range of the external bias current at S130, the reference cell trimming terminates.
Returning to S130, if the reference cell current measured by the tester is not within the given error range of the external bias current, the tester may perform manual trimming of the reference cell at S140. When manually trimming, the reference cell of the semiconductor memory device may be programmed based on a program bias voltage (e.g., a voltage applied to the source, the gate, and the drain of the reference cell) supplied by the tester at S142, and the reference cell current of the programmed reference cell may be measured by the tester at S144. When the measured reference cell current has a requested current value (e.g., when the measured reference cell current is within a given error range of the external bias current) at S146, the manual trimming terminates. Returning to step S146, when the measured reference cell current is not within the given error range, the manual trimming may be repeated. The manual trimming may be repeated by changing the program bias current supplied by the tester.
FIG. 2 is a block diagram of a conventional semiconductor memory device 200 for performing the reference cell trimming illustrated in FIG. 1. Referring to FIG. 2, the semiconductor memory device 200 may include a reference cell 210, an I/O pad 215, a first comparator 220 and a voltage supply controller 230. During automatic trimming of the reference cell 210, the reference cell 210 may be programmed based on a bias voltage Vpg1 supplied by the voltage supply controller 230.
A reference cell current Iref1 may flow between a drain and a source of the reference cell 210 based on the bias voltage Vpg1. The first comparator 220 may compare an external bias current Ix input via the I/O pad 215 with the reference cell current Iref1 and output a comparison signal ST. The voltage supply controller 230 receives the comparison signal ST and may supply the bias voltage Vpg1 to the reference cell 210 based on the comparison signal ST.
In the conventional reference trimming in a conventional semiconductor memory device, a parasitic component may cause errors when the external bias current is supplied by the tester during the automatic trimming, which may decrease accuracy of the automatic trimming. In addition, to measure the reference cell current of each of a plurality of reference cells in the conventional semiconductor memory device during manual trimming, a parametric measure unit (PMU) in the tester may individually contact each reference cell, and thus, trimming test time for the reference cells in the semiconductor memory device may increase.